1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (abbreviated as semiconductor IC hereinafter) and, more particularly, to a semiconductor IC consisting of MOS transistors (MOS ICs) adapted to the requirements of multifunction and high speed operation.
2. Description of the Prior Art
MOS ICs, that are currently in most general use, receives a power supply voltage of 5 V and includes MOS transistors having a threshold voltage of about 0.7 V and a gate length of about 1 .mu.m as a typical size, in order to communicate with transistor-transistor-logic (TTL) circuits, to uniform their fabrication processes, or the like. Of late, however, demands for multifunction and high speed of semiconductor ICs are strong, and developments to satisfy these demands are in progress.
In order to realize the multifunction and high speed operation, technologies for enhancing fine geometry of the circuit elements and for raising the level of integration based on the fine geometry are indispensable, and a great deal of effort is being expended on them. As a result, the refinement is proceeding in the gate length, for example, from the above-mentioned value of 1 .mu.m to 0.6 .mu.m, and further to 0.35 .mu.m. Moreover, in order to realize a high speed operation, it is convenient to reduce an amplitude of a signal to be handled. For this purpose, the operating voltages for various parts are lowered (that is, reduction of voltages). The reduction of voltage is proceeding in the supply voltage for example, from the above-mentioned value of 5 V to 3.3 V, and further to 2.5 V.
Accompanying the reduction of voltages, there is required lowering of the threshold voltage of the transistor (referred to as threshold voltage reduction hereinafter) for discrimination of high level and low level of signals. The threshold voltage reduction is proceeding, for example, from the above-mentioned value of 0.7 V to about 0.2-0.4 V.
The improvement of technology for fine geometry enables the realization of fine geometry of circuit elements and wirings through which it contributes to the reduction of the propagation time of carriers, namely, to the increase of the operating speed of the transistors. On the other hand, the reduction in the electrode spacing urges to make the insulating film thin, which requires the reduction of voltage for securing the reliability. The reduction of voltage leads to reduction of power consumption which in turn enables high integration. In this way, the multifunction and the high operating speed of semiconductor ICs are realized by the unifined interaction of technologies for fine geometry, voltage reduction, thereshold voltage reduction, high integration, and the like.
The aforementioned threshold voltage reduction can be realized by the technique of selecting various parameters at the design and fabrication stages such as selection of sizes for various parts, control of impurity concentrations, or the like of the transistor, the technique of applying a forward bias voltage to the junction part between a semiconductor substrate (or a P-well or an N-well within the substrate, and similarly hereinafter) and the source region of a transistor formed on the surface of the substrate, and the combination of these techniques (see, for example, "A New CMOS Structure for Low Temperature Operation with Forward Substrate Bias", IEEE 1992 Symposium on VLSI Technology Digest of Technical Papers).
The signal processing operation of the semiconductor ICs employing transistors with threshold voltage reduction is hardly affected in the normal operation mode even when there are induced noise, temperature change, or the like in the ground wiring and power supply wiring, since signal processing operation such as data rewriting is executed in response to a system clock. However, in a standby mode in which the system clock is stopped being supplied to hold an internal condition, the potential difference between the channel formation part of the transistor and the substrate (well) is small, so that, the carriers within the channel reach the substrate (well) by going over the energy barrier for the channel through acquisition of slight energy from induced noise, temperature change, or the like, preventing the carriers from the source electrode to arrive at the drain electrode. Consequently, there occur malfunctions, such as variation, inversion, or the like, or faulty data holding of the binarized values to be held by the transistor, namely, the level of the data. Moreover, since the induced noise easily exceeds the threshold voltage of the transistor, level inversion of held data tends to occur.
As a technique for solving these problems in the standby mode, there is frequently adopted a method of raising the threshold voltage of the transistor by applying a reverse bias to the substrate (well) where the transistor is formed. However, according to the technique, there are required a reverse bias generating circuit, wirings for supplying the reverse bias, and the like, creating power consumption by the reverse bias generating circuit itself, and power consumption by the wirings and the substrate (well), and the like due to the very fact that they are parts of a semiconductor device. In particular, in semiconductor ICs of the type which back up the standby mode by batteries, the life of the batteries is reduced conspicuously.